1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to semiconductor structures and their methods of fabrication.
2. Discussion of Related Art
In order to increase the performance of modern integrated circuits, such as microprocessors, silicon on insulator (SOI) transistors have been proposed. Silicon on insulator (SOI) transistors have an advantage in that they can be operated in a fully depleted manner. Fully depleted transistors have an advantage of ideal subthreshold gradients for optimized on current/off current ratios. An example of a proposed SOI transistor which can be operated in a fully depleted manner is that of a tri-gate transistor 100, such as illustrated in FIG. 1. Tri-gate transistor 100 includes a silicon body 104 formed on insulating substrate 102 having buried oxide layer 103 formed on a monocrystalline silicon substrate 105. A gate dielectric layer 106 is formed on the top and sidewalls of the silicon body 104 as shown in FIG. 1. A gate electrode 108 is formed on the gate dielectric layer and surrounds the body 104 on three sides essentially providing a transistor 100 having three gate electrodes (G1, G2, G3) one on each of the sidewalls of the silicon body 104 and one on the top surface of the silicon body 104. A source region 110 and a drain region 112 are formed in silicon body 104 on opposite sides of gate electrode 108 as shown in FIG. 1. The active channel region is the region of the silicon body located beneath gate electrode 108 and between the source region 110 and drain region 112. An advantage of a tri-gate transistor 100 is that it exhibits good short channel effects (SCEs). One reason tri-gate transistors 100 exhibit good short channel effects is that the nonplanarity of such devices places the gate electrode 108 in such a way as to surround the active channel region on all three sides.